1. Field of the Invention
This invention relates to processors and to circuits and methods for fetching instructions in order for execution.
2. Description of Related Art
An instruction fetch unit in a processor fetches instructions from memory for execution by an execution unit in the processor. Ideally, an instruction fetch unit obtains the instructions in program order, at a rate that avoids any idle time for the execution unit and therefore maximize processor performance. However, a high instruction fetch rate may be difficult to achieve because memory that stores instructions is often much slower than the execution unit.
Instruction caches provide a fast but small memory for instructions and can increase the speed of instruction fetches. However, with an instruction cache, a delay still occurs if there is a cache miss when fetching a desired instruction, for example, when sequential instruction execution or taking a branch in a program requires an instruction that is not currently in the instruction cache. When a cache miss occurs, the instruction cache accesses external memory. If there is a delay while the instruction cache accesses the external memory, the execution unit may be idle which degrades processor performance. Accordingly, instruction fetch units are sought which minimize delays that might otherwise occur as a result of a cache miss.